1. Field of the Invention
The present invention relates to a level shifting circuit for converting a logical level.
2. Description of Related Art
FIG. 7 is a circuit diagram to show a conventional level shifting circuit. In a semiconductor device using two types of voltage sources, a low voltage source (VCCL) and a high voltage source (VCCH), the level shifting circuit serves as a circuit which converts the logical level of the voltage VCCL into the logical level of the voltage VCCH (VCCL less than VCCH). In FIG. 7, reference sign IN_L denotes an input signal having the logical level of the voltage VCCL, sign OUT_H denotes an output signal having the logical level of the voltage VCCH, signs INV0701_L and INV0702_L denote inverters operating by the low voltage source (VCCL), sign INV0703 denotes an inverter operating by the high voltage source (VCCH), signs MP0701 and MP0702 denote P-type transistors and signs MN0701 and MN0702 denote N-type transistors.
FIG. 8 is a waveform chart to show an operation of the conventional level shifting circuit.
Next, an operation will be discussed.
The operation of the level shifting circuit shown in FIG. 7 will be discussed below, referring to the waveform chart of FIG. 8. In the following discussion, the logic High level of the voltage VCCL is represented as xe2x80x9cH_lxe2x80x9d level, the logic High level of the voltage VCCH is represented as xe2x80x9cH_hxe2x80x9d level and the logic Low level (0 V) of these voltages are represented as xe2x80x9cLxe2x80x9d level.
In a state where the input signal IN_L is stationary at the xe2x80x9cLxe2x80x9d level, a node N0701 has the xe2x80x9cH_lxe2x80x9d level and a node N0702 has the xe2x80x9cLxe2x80x9d level, and the N-type transistor MN0701 is in an ON state and the N-type transistor MN0702 is in an OFF state. Further, a node N0703 has the xe2x80x9cLxe2x80x9d level and a node N0704 has the xe2x80x9cH_hxe2x80x9d level, and the P-type transistor MP0701 is in the OFF state and the P-type transistor MP0702 is in the ON state. The output signal OUT_H has the xe2x80x9cLxe2x80x9d level.
When the input signal IN_L changes from the xe2x80x9cLxe2x80x9d level to the xe2x80x9cH_lxe2x80x9d level (t0 of FIG. 8), the node N0701 comes into the xe2x80x9cLxe2x80x9d level and the node N0702 comes into the xe2x80x9cH_lxe2x80x9d level by the operations of the inverters INV0701_L and INV0702_L (1, 2 of FIG. 8) and the N-type transistor MN0701 comes into the OFF state and the N-type transistor MN0702 comes into the ON state. At this time, since the P-type transistor MP0702 remains in the ON state, the potential of the node N0704 falls to a voltage value V0 obtained by dividing the voltage VCCH by the ON-resistance of the P-type transistor MP0702 and the ON-resistance of the N-type transistor MN0702 (3 of FIG. 8). When the potential of the node N0704 becomes VCCHxe2x88x92VthP (VthP represents a threshold voltage of the P-type transistor) or lower, the P-type transistor MP0701 comes into the ON state and the node N0703 is charged up to the voltage VCCH (4 of FIG. 8) and when the potential of the node N0704 becomes the threshold voltage of the inverter INV0703 or lower, the output signal OUT_H becomes xe2x80x9cH_hxe2x80x9d level (5 of FIG. 8). Further, since the node N0703 is charged up to the voltage VCCH, the P-type transistor MP0702 comes into the OFF state and the node N0704 is completely discharged to 0 V (6 of FIG. 8).
When the input signal IN_L changes from the xe2x80x9cH_lxe2x80x9d level to the xe2x80x9cLxe2x80x9d level (t1 of FIG. 8), a series of operation is performed, almost like the above, where the node N0701 changes to the xe2x80x9cH_lxe2x80x9d level and the node N0702 changes to the xe2x80x9cLxe2x80x9d level (11, 12 of FIG. 8), the N-type transistor MN0701 comes into the ON state and the N-type transistor MN0702 comes into the OFF state, the potential of the node N0703 falls to V0 (13 of FIG. 8), the P-type transistor MP0702 comes into the ON state, the potential of the node N0704 rises up to the voltage VCCH (14 of FIG. 8), and then when the potential of the node N0704 becomes the threshold voltage of the inverter INV0703 or higher, the output signal OUT_H changes to the xe2x80x9cLxe2x80x9d level (15 of FIG. 8) and the potential of the node N0703 changes to 0 V (16 of FIG. 8).
As discussed above, there is a case in the conventional level shifting circuit, where the P-type transistor MP0701 and the N-type transistor MN0701 come into the ON state at the same time or where the P-type transistor MP0702 and the N-type transistor MN0702 come into the ON state at the same time (3, 13 of FIG. 8), and the voltage V0 of the node N0701 or the node N0702 at that time should be VCCHxe2x88x92VthP or lower. Assuming that the ON-resistance of the P-type transistor is RonP and the ON-resistance of the N-type transistor is RonN, since V0=VCCH*RonN/(RonP+RonN), it is necessary to satisfy a relation RonP greater than RonN in order to set V0 to a low value to some degree. Further, assuming that the channel width of a transistor is W and the channel length thereof is L, since the ON-resistance thereof is in proportion to L/W, it is necessary to set the channel width W smaller and/or the channel length L larger in order to increase the ON-resistance and it is necessary to set the channel width W larger and/or the channel length L smaller in order to decrease the ON-resistance.
Since the conventional level shifting circuit has the above constitution, since a gate-source voltage (VCCL) at the time when the N-type transistors MN0701 and MN0702 are in the ON state is lower than a gate-source voltage (xe2x88x92VCCH) at the time when the P-type transistors MP0701 and MP0702 are in the ON state, the ON-resistance RonN of the N-type transistor is hard to reduce even if L/W of the N-type transistors MN0701 and MN0702 is made smaller, and this tendency is accelerated as the difference between the voltage VCCH and the voltage VCCL becomes larger. Therefore,in order to satisfy the relation R on P greater than R on N, it is necessary to set the ON-resistance RonP extremely high. Since the nodes N0701 and N0702 are charged by the P-type transistors MP0701 and MP0702 (4, 14 of FIG. 8), however, the charging speed becomes lower when the ON-resistance RonP is extremely high, and this causes a problem that a delay time of the output signal OUT_H from the input signal IN_L may increase.
In contrast to this, though it is possible to satisfy the relation RonP greater than RonN with RonP kept low to some degree by setting L/W of the N-type transistors MN0701 and MN0702 extremely smaller than L/W of the P-type transistors MP0701 and MP0702, since a value (RonP+RonN) becomes small in this case, a through current which flows when the P-type transistor MP0701 and the N-type transistor MN0701 come into the ON state at the same time or the P-type transistor MP0702 and the N-type transistor MN0702 come into the ON state at the same time becomes large and this increases the power consumption.
The present invention is intended to solve the above described problems and it is an object of the present invention to provide a level shifting circuit which realized an increase of the potential difference allowing the logic-level conversion and a reduction of the delay time and the through current.
In the level shifting circuit in accordance with the present invention, a charging means is made up of a first P-type transistor and a second P-type transistor whose drains are connected to said first and second nodes respectively, whose gates are connected to said second and first nodes respectively and whose sources are connected to said second voltage source; a first switching circuit and a second switching circuit connected in parallel to said first and second P-type transistors respectively, and keeping an OFF state at a stationary state when said input signal does not change; and a charging regulator circuit which charges said second node to a logic xe2x80x9cHxe2x80x9d by setting said second switching circuit to an ON state and thereafter brings back said second switching circuit to an OFF state when said first node is changed from a logic xe2x80x9cHxe2x80x9d to a logic xe2x80x9cLxe2x80x9d by a change of said input signal, and charges said first node to the logic xe2x80x9cHxe2x80x9d by setting said first switching circuit to the ON state and thereafter brings back said first switching circuit to the OFF state when said second node is changed from the logic xe2x80x9cHxe2x80x9d to the logic xe2x80x9cLxe2x80x9d by the change of said input signal.
As discussed above, according to the present invention, since the ON-resistances of the first and second P-type transistors are set extremely high, a through current which flows when the first P-type transistor and the first N-type transistor come into the ON state at the same time or when the second P-type transistor and the second N-type transistor come into the ON state at the same time, can be made extremely small.
Further, even if the ON-resistances of the first and second N-type transistors become relatively large because the difference of the first and second voltage sources becomes large, it is possible to reduce the divided voltage value.
Furthermore, since no through current flows through the first and second switching circuits for charging the first and second nodes, it is possible to optimize the ON-resistances thereof with a high priority given to charging speed and avoid an increase in delay time caused by lower power consumption.
Thus, the present invention produces an effect of providing a level shifting circuit which increases the potential difference allowing the logic-level conversion and reduces the delay time and the through current.